A number of different design methodologies are known which enable a user to efficiently synthesize logic circuits. For example, one technique uses VHDL code to synthesize, or generate, efficient logic circuits. Another technique uses Verilog to synthesize efficient logic circuits.
VHDL refers to VHSIC Hardware Description Language. VHDL is a hardware description language (HDL) that is used to design electronic systems at the system, board and component levels. VHDL enables the development of models using a very high level of abstraction. Although VHDL was initially conceived as a documentation language, the language is presently used principally to perform simulation and logic synthesis operations. Although VHDL was originally developed for the Unites States military VHSIC program, VHDL is now identified as an Institute of Electrical and Electronics Engineers (IEEE) standard. VHSIC refers to Very High Speed Integrated Circuit, which is a category of ultra-high-speed chips that employ LSI and VLSI technologies.
Verilog refers to a hardware description language (HDL) that is used to design electronic systems at the system, board and component levels. Although originally developed by Cadence Design Systems, Inc., of San Jose, Calif., Verilog is now an IEEE standard that is a de facto standard for proprietary HDLs.
VHDL and programmable logic design process implementations include the creation of design descriptions, and involve synthesis, placement and routing of integrated circuits, as well as the creation of test benches in order to verify generated designs.
A test branch, sometimes referred to as a test fixture, is a simulation model that is used to verify a design's functionality. The test bench allows application of input test vectors to a design entity (such as an integration circuit under test), and verifies output of the simulation model. A test bench can be used to simulate a pre-synthesis design description, or a post-layout design description.
The ability to provide an integrated circuit, wherein an entire system is provided on a single chip, greatly complicates testing of the chip. The ability to implement design-for-test techniques becomes especially important when an entire system is designed onto a single, common chip. Accordingly, the ability to efficient and effectively test a chip is very important. Typically, system-on-a-chip designs utilize reusable cores, or cells. Use of these cells has further complicated the ability to test a chip because, until recently, core-based design-for-test (DFT) and “testability” efforts have been directed almost exclusively to use with digital chips. However, the implementation of full system-on-a-chip designs has lead to designs that also include analog block or cells These chips are referred to as “mixed-signal” chips. Traditional test bench designs have not been able to efficiently and effectively test such “mixed-signal” chips.
Recent efforts are being directed in order to provide some limited success when testing “mixed-signal” chips. For example, IEEE P1149.4 Mixed-Signal Test-Bus Working Group is presently designing a standard as an extension of a well-known 1149.1 boundary-scan standard to include on-chip analog structures. See Cron, Adam, “IEEE P1149.4—Almost a Standard,” 1997 International Test Conference Proceedings, Nov. 3-7, 1997, p. 174 IEEE P1149.4 will be configured to use a six-wire bus to measure analog signals. Four conductive lines of the bus correspond to the four lines presently used by the IEEE existing 1149.1 bus at the test-access port (TAP). Two additional wires cooperate to provide an analog stimulus-and-response bus, referred to as analog TAP. This analog TAP bus connects with analog test equipment, such as analog components of a chip.
One technique recently realized for testing “mixed-signal” chips was introduced by Logic Version, of San Jose, Calif., and involves a technique for testing embedded analog cores with small built-in self test (BIST) blocks that comprise synthesizable Verilog or VHDL code. By placing these blocks on a mixed-signal chip, a way is provided to digitally test analog cores while sometimes eliminating any need for analog test equipment. However, separate analog test equipment is still needed in many cases. Furthermore, iterative testing still remains complicated and time-consuming.
Another technique using analog and mixed-signal DFT and testability tools is provided by OpMaxx, Inc., of Beaverton, Oreg., sold under the trade name of DesignMaxx. DesignMaxx is provided for measuring analog circuit sensitivity to direct current (DC), alternating current (AC) and transient simulation. One component is tailored for analog fault-coverage analysis, and another component is tailored for generating analog tests and detecting hard and soft faults in analog circuits. However, OpMaxx may not be able to handle all chips containing embedded mixed-signal cores. Additional details of OpMaxx are available from Arabi, Karim and B. Kaminska, “Oscillation Build-In Self Test (OBIST) for Functional Structural Testing of Analog and Mixed-Signal Integrated Circuits,” 1997 International Test Conference Proceedings, November 3-5, 1997, P. 768.
Yet another technique for testing analog cells embedded in mixed-signal products is provided by Philips Semiconductors, of Sophia Antipolis, Valbonne, France. An Analog Test Access Port (ATAP) is provided such that the testing of analog cells is made independent of the logic circuitry around which each analog cell is embedded. The Analog Test Access Port (ATAP) is an auxiliary port implemented at an analog cell level that provides access to all the cell's digital I/O's, such as Clock, Reset, Data Pins, configuration bits, etc., when the cell is set into a dedicated analog test mode. Details of such Analog Test Access Port (ATAP) are disclosed in Applicant's U.S. Pat. application Ser. No. 09/109,848, filed Jul. 2, 1998, entitled “Analog Test Access Port and Method Transfer”, and incorporated herein by reference.
For integrated circuits (ICs) containing analog and mixed signal cells, all the analog and mixed signal cells that contain ATAP should be tested using the ATAP protocol. In order to ensure that the cells within the IC are well connected, a simulation should be run before testing the IC. The simulation consists mainly in writing values into the ATAP registers in order to set the cell into a defined status. When the simulation is done, measurements can be made. Accordingly, a series of successive write operations are made which depend on the cell. For each IC containing cells with ATAP, the signal names are different and manually wrting a test bench requires a considerable amount of effort and time.
In the past, analog test access port (ATAP) test benches have been used to test for interconnection between circuits. These test benches were very basic since they were written by hand. Therefore, there was a relatively high risk of errors in the instructions and a non-negligible time was need to debug the design.
Therefore, there exists a need to provide an improved apparatus and method for generating test benches, and for improving test program generation.